The advancing complexity of up to date microelectronics has motivated research in high-level and system synthesis (HLS). Formal and intelligent HLS techniques are presented during this contribution, thus the generated implementation is correct-by-construction. These intelligent techniques include RDF (Resource Description Framework) and logic relations, along side automatic implementation options and that they are employed for the transformations of a hardware compiler. The proposed toolset utilizes compiler-generators, RDF rules and logic programming together with XML validation of the interior state of the compiler. These intelligent and formal techniques make the entire transformation from ASCII text file to implementation, formal. The HLS tool is enhanced with the Parallel, Abstract Resource – Constrained Scheduler, which aggressively optimizes the initial state schedules, into maximally parallelized ones.
